Data transmission between LSIs (Large Scale Integrations) is implemented based on serial transmission of transmitting data packet via a plurality of signal lines with a transmission path being configured to attain a faster speed, which is on the verge of becoming a mainstream.
Note that the data transmission involves, as the case may be, attaching an error correction code to the data in order to correct this error when an error occurs.
In the serial transmission, however, a multiplicity of error bits might occur consecutively due to a burst error, and hence a multiplicity of error correction codes is required for enabling the error bits to be corrected when the burst error occurs. Consequently, the attachment of the error correction codes in the serial transmission causes decreases in throughput and in latency.
Such being the case, the data transfer device on the transmission side has hitherto generated a CRC (Cyclic Redundancy Check) code on a packet-by-packet basis of transmission data and transmits a packet with the CRC code inserted, and a data transfer device on the side of a reception unit performs the CRC of the received packet. Namely, the data transfer device detects as to whether the received packet contains an error or not and makes the correction by retransmitting the packet without correcting the error even if there is the error.
Moreover, technologies disclosed in the following Patent documents are given by way of the prior arts related to the invention of the present application.    [Patent document 1] Japanese Laid-Open Patent Publication No. H10-65655    [Patent document 2] Japanese Laid-Open Patent Publication No. H09-307510